This invention relates to a bit buffer system used when a plurality of coded data signals are multiplexed.
Since, when a plurality of coded data signals are multiplexed, there is no predetermined synchronous relation between each coded data signal and a multiplexed signal, a bit buffer system is generally utilized for matching different timing between the coded data signal and the multiplexed signal in order to multiplex the coded data signals each of which runs on on the basis of independent timing.
The drawbacks of the conventional system are first described with reference to FIGS. 1 to 4. As shown in FIG. 1, coded data signals SD.sub.1 transmitted from a data terminal apparatus or the like are sent to a bit buffer BB through an interface IF and, further, a timing pulse ST.sub.1 which controls the period of transmission data signals SD.sub.1 and a transmission request signal RS which is generated concurrently with the transmission data signals SD.sub.1 and which instructs the transmission to a multiplexor MP or a receiving unit are taken out via the interface IF.
The bit buffer BB comprises a shift register SR having a predetermined stages, 8 stages #1 to #8 in this example, and sequentially stores 8 bits of transmission data signals SD.sub.1 in accordance with the timing pulse ST.sub.1. Either one of outputs of #1 to #8 stages of the shift register SR is selected by a data selector DS. At the time of initializing to be described later, a transmission data signal SD.sub.1 is taken out of either #4 or #5 stage which corresponds to a substantial central stage and supplied to the multiplexor MP as a coded data signal SD.sub.2.
The data selector DS is controlled by the output from an up-down counter CT (termed as U/D counter hereinafter) to select a specified stage of the shift register SR from which the transmission data signal SD.sub.1 is taken out. The U/D counter is adapted to count either up "U" or down "D" count stepwise according to the phase difference between the timing pulse ST.sub.1 and a timing pulse ST.sub.2 controlling the operation of the multiplexor MP.
More particularly, the phase difference between the timing pulses ST.sub.1 and ST.sub.2 is detected by a phase detector PD such as a phase comparator and when the phase of the timing pulse ST.sub.2 leads the timing pulse ST.sub.1, one down-output D is produced from the phase detector PD at the time when a predetermined relation occurs between ST.sub.1 and ST.sub.2 as will be described later while, on the other hand, when the phase of the timing pulse ST.sub.2 lags, one up-output U is produced at the time when another predetermined relation between ST.sub.1 and ST.sub.2 takes place, whereby the U/D counter carries out up "U" or down "D" count for one step.
The U/D counter CT is preset for initializing by a preset pulse which is produced from a pulse generator PG when it detects the leading edge of the transmission request signal RS. In the example shown in the figure where a binary counter of 3 bits is utilized, this counter is so initialized that the count output is made a binary of either 1.0.0. or 1.0.1, in other words either 4 or 5 in decimal, to control the data selector DS, and a transmission data signal SD.sub.1 is taken out of the stage #4 or #5 of the shift register SR.
Accordingly, the bit buffer BB operates as shown in time charts of FIGS. 2 and 3 to achieve the intended purpose. This will be described in more detail. FIG. 2 shows the case where the period of the timing pulse ST.sub.2 is shorter than that of ST.sub.1 and the timing pulse ST.sub.2 leads ST.sub.1. It is assumed that bits A to F of the transmission coded data signals are sequentially stored in the shift register SR according to the timing pulse ST.sub.1 and taken out from the stage #4. Since the transmission coded data signal is converted into a transmission output SM by fall of the timing pulse ST.sub.2, bits A and B are converted into normal transmission outputs SM but at bit C, the fall takes place twice within the period of bit C because one period of ST.sub.2 is confined in one period of ST.sub.1. Therefore, as indicated in the figure at (SM), the bit C is transmitted twice causing errors in transmission.
However, when the fall of the timing pulse ST.sub.2 takes place for the first time at low level (termed as "L" hereinafter) of the timing pulse ST.sub.1, the phase detector PD generates a down-output D to shift the specified stage of the shift register SR from which the transmission coded data signal SD.sub.1 is taken out by the data selector DS, from stage #4 to stage #3 in this example. As a result, due to the fact that bit C has been stored in the stage #4 and the following bit D in the stage #3, the bit D can be taken out and transmitted following the bit C as shown in the figure at SM, thereby preventing the erroneous transmission.
In the case where the period of ST.sub.2 is larger than that of ST.sub.1 and the phase thereof lags, the fall does not take place at the bit D of the transmission coded data signal SD.sub.1 as shown in FIG. 3 and, therefore, if it were transmitted as it is, the bit D would be dropped as shown in the figure at (SM) to cause erroneous transmission. The erroneous transmission is avoided in a manner that the phase detector PD generates an up-output U when the fall of the timing pulse ST.sub.2 first takes place at high level (termed as "H" hereinafter) of the timing pulse ST.sub.1 to shift the specified stage of the shift register SR from stage #4 to stage #5 so as to take out the preceding bit D stored in the stage #5 and to transmit the bit D following the bit C as shown as SM, thereby ensuring the normal transmission.
The prior art bit buffer BB operates and carries out the matching operation between the transmission data signal SD.sub.1 and the transmission output SM of which timings are different from each other in a manner described in the foregoing. However, since the aforementioned operation is repeated to shift the specified stage from which the transmission coded data signal SD.sub.1 is taken out repeatedly toward stage #1 or #8 as far as the frequency difference between the timing pulses ST.sub.1 and ST.sub.2 is constant, the specified stage eventually reaches either the stage #1 or the stage #8 and can not proceed any more, causing such a defective transmission as transmitting the same bit repeatedly as shown in FIG. 2 at (SM) or as bit missing as shown in FIG. 3 at (SM).
More particularly, as shown in FIG. 4, if initialization IR starts only when the transmission request signal RS shifts from "L" to "H" and if the frequency difference between the timing pulses ST.sub.1 and ST.sub.2 is constant, a period t for which erroneous transmission ER takes place is determined by the frequency difference. The erroneous transmission takes place repeatedly at the period t starting from the initialization IR. Then, even if erroneous transmission does not take place in a group DT.sub.1 of the data bits, erroneous transmission ER does take place in a group DT.sub.2 of the data bits given as shown in the figure.
The erroneous transmission can be avoided if a predetermined number of the stages of the shift register SR is increased, but it not only complicates the system but also pushes up the cost, resulting in undesirable disadvantages in practice. It can also be avoided by dividing the transmission coded data signal SD.sub.1 and turning on or off the transmission request signal RS each time that the divisional group of transmission data signal occurs for sending all the data bit groups at the same initialization timing as the bit group DT.sub.1. But this expedient will inconveniently prolong the time required for transmission as well as reduce the operational efficiency of the system and the transmission line circuit.